Used to generate clocks in most VLSI designs, the phase-locked loop (PLL), is often a 
feared and misunderstood beast. Black-box designs from IP vendors are integrated on-
chip with little understanding of the PLL's sensitivities to process and digital noise. 
Inexperienced designers read the latest literature and try to hit a "home run" with their 
first PLL. Ignorance of the PLL's internal workings may lead to impossible-to-meet 
specs and inadequate test features. This tutorial provides a practical introduction to basic 
PLL design for clock generation, including feedback stability, common circuit 
implementations, spec writing, and design for test.  Examples of PLL "gotchas" and real-
world failures are presented.