Q. With my mathcad files, I chose a Phase Margin=60
degrees and the corresponding Zeta=0.92. I designed
this for a ratio of 20% beetween my third and forth
pole in the denomiator of G(S). So I believed that my
system should be stable. Then I went ahead and
verified this using matlab sims. Data looked awsome. 

But when I went to Cadence simulations, PLL never
locked. My Charge Pump is nearly matched. VCO has good
linearity over the range of interest. I am using ideal
Caps and Resistance to debug ths issue. The control
voltage approaches the voltage required for locking
and then has a near sinusoidal very low frequency
ripple on it. Since the simulation environment is near
ideal and Matlab looks perfect, the problem has
stumped me.( By the way I am using an acquisition aid
too which turns off when Vcontrol reaches near the
voltage required for lock.) 

Kvco=260Mhz/V and N=156.

I will appreciate if you can give any inputs or
suggestions!!!

A. Using R=20k, C1=400pF, C2=20-40pF, I confirmed
that the transient behavior of your PLL is good. 
So, it's a circuit problem, not a loop problem,
as long as your actual circuits are close to
your calculated loop parameter values.

You didn't say what is the frequency of the
small control voltage oscillation? Is it near
the expected natural frequency of the loop?
Is it near the reference frequency? Is the
oscillation amplitude constant or is it 
slowly dying out? Are you adding any noise
sources to your simulations?

I'd look at the following, depending on your topology.

0) If you initialize the control voltage and
then open-loop the PLL (disable the PFD), is there
still an oscillation? If it's still there, it's
not feedback clock related. 

1) If you change a loop parameter significantly
(e.g. C1, R, Icp), does the oscillation change?
If it's loop related, it should.

2) Is an internal feedback loop (e.g. V2I) 
oscillating? Usually these oscillations are
fairly high frequency. e.g. > 10 MHz

3) Is there an internal feedback loop you missed
in your analysis that is adding a parasitic pole? 
e.g. V2I capacitance, self-bias Icp?

4) Is there are a start-up circuit that is partially
turning on and off? e.g. acquisition circuit.

5) Are you biasing a transistor so close to the Vt
that it is partially shutting on and off?

6) Is the effective Icp larger than expected due
to switch feedthrough? This would lead to control
voltage glitches, not oscillation.

7) If you reduce the feedback divisor with the same
VCO frequency, does the oscillation change? How about
keeping the feedback divider the same but changing
the reference frequency?

8) I don't believe that PFD/ChargePump dead-zone
is causing your problem, but it's something
that can cause phase error to slowly drift
back and forth. In general, I wouldn't expect
this to cause much change on Vctl. 

And the problem is....(as usual) the feedback divider.

From the designer's own words:

In my latest sims I noticed that the control voltage variations are
not periodic but they are more random in nature
(looked somewhat like dithering signal). I broke the
loop and supplied an ideal clock to the phase
detector, and the variations disappeared. So I knew
the problem is coming from DivideBy156 in the feedback
loop. My colleague made this divide by block using CML
dividers to generate this division. I was waking up
the VCO from the floor frequency. At this slow
frequency edges were very sloppy and CML divider was
not generating the right division. Then I introduced a
buffer stage in between and now the division was right
but still it was giving lot of glitches. I replaced
that with another modular divider based on TSPC flops
and it worked. ( Still need to figure out what was the
problem with CML gates.) Once the PLL acquired lock, I
compared the locking process to my calculations and
was happy to see that they matched well.