Q) How do you introduce jitter in the simulation?
I notice that for jitter due to supply variation,
some people input a square wave of a particular frequency
and amplitude with certain rise/fall time. Does it matter
much the frequency of the square wave?
A: There are many jitter sources that you may add to
your simulations. In my BEHAVIORAL simulator,
I add noise at the reference, reference
divider, phase detector, charge pump, low-pass filter
caps, VCO, and feedback divider. Basically, I add
noise to every component. Since I use the behavioral
simulator primarily to determine loop behavior, the
most important noise source is the reference.
The noise sources may be random (Gaussian), sine,
square, or piece-wise linear.
In circuit simulation (spice), I focus on supply
noise because this is the noise source that I'm
working hardest to reject.
If I were to run only one closed-loop simulation,
then I'd add a square wave to VDD at the natural
frequency of the PLL since the PLL tends to
over-compensate (peak) at this frequency.
1) The sharp edge (~ 1 ns) of the square wave tends
to create worst-case VCO period jitter.
2) The square waves's long high time allows
the resulting change in VCO frequency (due to dVDD)
to accumulate as phase error.
3) The modulation at the natural frequency tends to
excite the PLL's peaking.
If you allow me to run one more closed-loop spice
simulation, then I'll use a piece-wise linear
function to delay the reference by almost one
reference period AFTER the PLL has locked.
I'll watch how the PLL reacts to this instantaneous
phase step, looking for
1) max amount of VCO overshoot
2) min amount of VCO undershoot
3) time to re-lock
4) number of control voltage oscillations
before re-locking.
I can estimate the natural frequency and
damping factor from these simulation results.