Q: What are the effects of dividing the VCO output by 2 on phase error?
A: Short answer. It depends.
The phase error (difference between reference and feedback clocks seen
at the phase detector) is a function of several factors. Let's assume
for the moment that the reference is perfect and that the sole source
of phase error is accumulated VCO noise.
Phase Error Factors:
1) the magnitude of VCO noise
2) how the VCO noise accumulates (random or deterministic?)
3) how fast the PLL feedback loop can respond to the accumulated VCO noise
and cancel it out
4) the magnitude of PLL feedback peaking
For RANDOM VCO noise, a rule of thumb for estimating phase error
(assuming the PLL is reasonably well-damped: 0.7 < damping < 1)
is the following:
PhaseError = RmsVcoJitter * sqrt (f(vco)/PLLbandwidth)
That is, VCO jitter integrates as phase error with the
square root of the ratio of VCO frequency to PLL bandwidth (BW).
In short, the more VCO cycles that occur before the loop can correct,
the more error that accumulates. Phase error is also linearly
proportional to the magnitude of the the VCO jitter.
Dividing the VCO by 2 requires the feedback multiplier to be
doubled since the VCO need to run twice as fast. So, that should
increase the phase error. Also, the PLL bandwidth DECREASES with
increasing feedback multiplier. That should increase the phase error
further.
Let's assume for sake of argument that PLL bandwidth is proportional
to the square root of the ratio of VCO gain to feedback divisor.
BW ~ sqrt(Kvco/M)
Note: the real relationship is probably between sqrt(Kvco/M) and Kvco/M,
depending on how damping factor is maintained.
Let's also assume that the VCO noise is random. i.e. no strong frequency
components in the noise sources.
Below, we analyze phase error vs. VCO divider (1 or 2) for three different
scenaria:
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1) If VCO gain and jitter remain constant w/VCO divider (not likely), then phase
error INCREASES by 70% when we divide the VCO by 2.
Repeating from above:
PhaseError = RmsVcoJitter * sqrt (f(vco)/PLLbandwidth)
PhaseErrorRatio(div2/div1) ~ 1 * sqrt(2/sqrt(1/2)) = 1.7
Phase error increases because f(vco) increases and BW decreases
2) If VCO gain remains constant and VCO jitter decreases with VCO frequency
as expected, then phase error DECREASES by 15% when we divide the VCO by 2.
PhaseErrorRatio ~ 1/2 * sqrt(2/sqrt(1/2)) = 0.85
This is a realistic scenario corresponding to the case where we increase
the control voltage to achieve the higher VCO frequency. The most
important factor is the decrease in VCO jitter at the 2X higher frequency.
3) If we increase the VCO gain by 2X in the divide-by-2 case to keep the
control voltage constant, then the PLL bandwidth remains unchanged (Kvco/M).
So, any change in phase error is the result only of changes in the magnitude of
VCO jitter, which decreases with frequency. So, phase error DECREASES by 30%
in this VCO div-by-2 scenario.
PhaseErrorRatio ~ 1/2 * sqrt(2/sqrt(1)) = 0.7
This scenario may be just a bit optimistic as it is often difficult to
keep PLL damping and bandwidth constant as the feedback multiplier changes.
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Thus far, we've looked at the effect of RANDOM noise on phase error.
What about deterministic noise?
If the PLL sees large deterministic noise at one or a few discrete frequencies,
then the above phase error estimates are invalid. With detministic noise,
you use the PLL transfer function to estimate how much VCO period
modulation accumulates as phase error before the feedback loop reacts.
For simplicity, let's assume deterministic noise occurs in one of
three frequency regimes:
1) For deterministic VCO noise at frequencies much higher than the
bandwidth of the PLL,
PhaseErrorRatio ~ 0.5*VcoJitter*f(vco)/fnoise = 0.5 * 2/1 = 1
In this scenario it doesn't matter if you divide the VCO by 1 or 2. The
phase error is the same as long as VCO jitter decreases as the frequency
increases.
Notice that there is no relationship to PLL bandwidth since the deterministic
noise goes away long before the feedback loop can react. Also, notice that
the sqrt() factor is gone. In any case, phase error tends to be small since
jitter has little time to accumulate.
The factor of 0.5 accounts for the fact that the noise accumulates in one
direction for only 1/2 the noise period.
2) For deterministic VCO noise much lower than the bandwidth of the PLL,
almost no phase error is seen since the PLL can correct for the noise
faster than it can accumulate. Think spread-spectrum clocking (~30kHz).
Also, in this case it doesn't matter if you divide the VCO by 1 or 2.
3) For deterministic VCO noise closer in frequency to the bandwidth of the PLL,
the feedback loop will track some of the noise and reject the rest.
If VCO jitter decreases with frequency as expected, then phase error is
largely a function of PLL bandwidth.
If PLL bandwidth decreases in the div-by-2 case (because the VCO gain
remains constant), then phase error INCREASES by about 40%.
PhaseErrorRatio = 0.5*VcoJitter*f(vco)/BW = 0.5 * 2/sqrt(1/2) = 1.4
If the VCO gain increases by 2X to maintain the PLL bandwidth, then
error is independent of VCO divider.
PhaseErrorRatio ~ 0.5*VcoJitter*f(vco)/BW = 0.5 * 2/sqrt(1/2) = 1.4
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We also need to take into account the effect of dividing the VCO on
the damping factor. Noise close to the PLL bandwidth typically results
in over-correction by the feedback loop. This "peaking"
is strongly dependent on the damping factor. Extremely low or
extremely high damping factors result in larger phase errors than predicted
by the above analysis.
Note: the relationship between damping and divider is sqrt(Kvco/M).