Q: What are some of the most effective approaches
people use to minimize jitter from both design and
layout?

A: I'm glad you asked about jitter and not phase error.
Jitter is much easier to analyze. Why? I believe
that most PLL jitter results from power supply noise
at much higher frequency than the bandwidth of the
PLL.
That means, to first order, you can ignore the
fact that the PLL is a feedback system.

Where does this power supply noise come from and
what can you do about it? The noise is due to the
fact that the current consumption of most synchonous
digital systems is not constant. In a microprocessor,
a cache miss may result in a number of clock cycles
in which most state machines are idle,
and then as Emeril says, BAM!, when the missing data
arrives, you see a current spike approaching tens of
Amps.

You can add explicit decoupling caps to the
power-supply and use flip-chip to reduce inductance,
but you still may see power-supply changes of 100mV or
more at frequencies exceeding 100MHz.

So, by far the most effective technique for reducing
sensitivity to power-supply noise is to use a voltage
regulator, usually bandgap-based. This requires that
the PLL has a separate power-suppy and that the
voltage level of this separate supply is more than
400mV higher than the voltage that you need for your
PLL.

For example, if you're in 130 nm and you want the PLL
to run at 1.2V, you'd want the PLL's power-supply to
run at probably 1.8V.

The voltage regulator typically consists of a

1) bandgap voltage reference. Provides stable
reference for the regulator.
2) a unity-gain amplifier consisting of a single-stage
amplifier (> 40dB DC gain) connected to a driver,
either a common-source amplifier (PMOS) or
source-follower (NMOS). Provides good power-supply
rejection
up to maybe 50MHz.  
3) lots of mosfet decoupling cap (between 200pF and
500pF) for high frequency power-supply rejection.

Beyond the voltage regulator, the most effective
design techniques for reducing jitter are to add 
a few pF of decoupling capacitance to the virtual
power-supply of a current-starved inverter based VCO.
Maneatis has started to do this even for his
differential-pair based VCO.

A third design technique is to ensure that the ripple
on the control voltage is not too large or does not
reach the VCO. Increasing the C2 smoothing cap in the
LPF helps. More effective is adding a V2I
between the control voltage and the ring oscillator
which filter high-frequency control voltage ripple.
See Maneatis' replica bias scheme for an example.

From the layout perspective,

1) Keep your sensitive analog nets away from digital
signals or use VSS or VDD shielding as appropiate.

2) If an analog net is referenced to GND, then use
GND, not VDD, as the shield. Same for decoupling caps.

3) Extract your PLL and write a script to check for
coupling to sensitive analog nets. I have a script
that does this and use it for every tapeout.
Otherwise, you'll miss something with visual
inspection alone. A script also save time.

4) Over-design your power-supply grid so that GND
is the same everywhere. You don't want IR drops
to cause mismatch among current mirrors.

5) At 130nm and below, the wavelength of the light
used to expose the wafer is too long to correctly
image the poly gates without OPC (optical proximity
correction). You need to help out the OPC tool by
keeping the the neighborhood around matching circuits
completely identical.

For example, if you have a current source that is
broken into 4 fingers, add a dummy poly to both
the left and right sides to guarantee that all four
fingers are exactly the same size. Otherwise, the
fingers on the ends will image differently than the
middle fingers.

6) More OPC. Lay out all poly gates in the same
direction for better matching. I mean all poly in
the entire PLL.

7) More OPC. Do not place high-density poly right
next to low-density poly. Example, don't place
long-channel decoupling caps right next to min L
ring oscillator cells. Abrupt changes in poly density
cause imaging problems.

8) Final OPC. Try to keep minimum channel length
poly gates on the same pitch. For example, do not
pushing the NMOS pulldowns in a NAND gate closer
together because you don't need to allocate space 
for a contact.